Reductions in the size and inherent features of semiconductor devices, for example, metal-oxide semiconductor (MOS) devices, have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS device and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of MOS devices, stresses may be introduced in the channel region of a MOS device to improve its carrier mobility, which in turn causes the improvement in saturation current, and hence the speed. It is desirable to rearrange interconnect metal scheme and allow higher device density.
However, interconnection between metal layers can be troublesome. In order to build connection between two metal layers in different levels, the arrangement of interconnect plugs may result in expanding in cell boundary. When cell boundary pushes outwardly, it also implies a smaller spacing between neighbouring components. The area of spare processing window reduces as the cell boundary enlarges, and subsequent manufacturing process may encounter spatial restriction.